By Douglas E. Ott
A Designer's advisor to VHDL Synthesis is meant for either layout engineers who are looking to use VHDL-based good judgment synthesis ASICs and for managers who have to achieve a realistic realizing of the problems serious about utilizing this expertise. The emphasis is put extra on sensible purposes of VHDL and synthesis in response to genuine reports, instead of on a extra theoretical method of the language.
VHDL and common sense synthesis instruments supply very robust functions for ASIC layout, yet also are very complicated and symbolize an intensive departure from conventional layout tools. this case has made it tricky to start in utilizing this know-how for either designers and administration, when you consider that an incredible studying attempt and `culture' switch is needed. A Designer's advisor to VHDL Synthesis has been written to aid layout engineers and different execs effectively make the transition to a layout method in keeping with VHDL and log synthesis rather than the extra conventional schematic established procedure. whereas there are various texts at the VHDL language and its use in simulation, little has been written from a designer's point of view on the way to use VHDL and common sense synthesis to layout actual ASIC structures. the fabric during this booklet relies on event won in effectively utilizing those ideas for ASIC layout and is based seriously on reasonable examples to illustrate the rules concerned.
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Additional resources for A Designer’s Guide to VHDL Synthesis
From experience, it is recommended that initially an expert individual or team of experienced digital design engineers with programming background be established as the pioneers in learning and applying this technology. The tasks of learning and evaluating the necessary tools, purchasing and putting those tools into place, and gaining hands on experience, are essential for a smooth transition into language-based design. The experts then can provide practical training for new users, including a high degree of initial support and confidence building.
This book will try to show good ways to design most common logic functions, but there are so many possible variations that it always pays to be aware of the synthesized results. Third, there could be a bug in the synthesis software that could result in excess gates in the design, even though it might work correctly, and you certainly will want to know about that so the vendor can correct the problem. The best general course of action is to keep an eye on the synthesized results in terms of gate efficiency.
Simulation is heavily used throughout the ASIC design cycle and typically uses a combination of VHDL for the actual design and the ASIC vendor's certified or "golden" logic simulator for the final design verification. For all of these activities, the same test patterns should be used for both sets of simulators, and the output results should be compared, to ensure that the final gate level ASIC design matches the original VHDL design. The simplest means of accomplishing this is to generate both sets of test patterns from the VHDL "test bench" used to simulate the VHDL design.